Silicon Labs /MGM210PA32JIA /SMU_S /PPUPATD0

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Interpret as PPUPATD0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EMU)EMU 0 (CMU)CMU 0 (HFXO0)HFXO0 0 (HFRCO0)HFRCO0 0 (FSRCO)FSRCO 0 (DPLL0)DPLL0 0 (LFXO)LFXO 0 (LFRCO)LFRCO 0 (ULFRCO)ULFRCO 0 (MSC)MSC 0 (ICACHE0)ICACHE0 0 (PRS)PRS 0 (GPIO)GPIO 0 (LDMA)LDMA 0 (LDMAXBAR)LDMAXBAR 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (TIMER2)TIMER2 0 (TIMER3)TIMER3 0 (USART0)USART0 0 (USART1)USART1 0 (USART2)USART2 0 (BURTC)BURTC 0 (I2C1)I2C1 0 (CHIPTESTCTRL)CHIPTESTCTRL 0 (LVGD)LVGD 0 (SYSCFG)SYSCFG 0 (BURAM)BURAM 0 (IFADCDEBUG)IFADCDEBUG 0 (GPCRC)GPCRC 0 (RTCC)RTCC

Description

Set peripheral bits to 1 to mark as privileged access only

Fields

EMU

EMU Privileged Access

CMU

CMU Privileged Access

HFXO0

HFXO0 Privileged Access

HFRCO0

HFRCO0 Privileged Access

FSRCO

FSRCO Privileged Access

DPLL0

DPLL0 Privileged Access

LFXO

LFXO Privileged Access

LFRCO

LFRCO Privileged Access

ULFRCO

ULFRCO Privileged Access

MSC

MSC Privileged Access

ICACHE0

ICACHE0 Privileged Access

PRS

PRS Privileged Access

GPIO

GPIO Privileged Access

LDMA

LDMA Privileged Access

LDMAXBAR

LDMAXBAR Privileged Access

TIMER0

TIMER0 Privileged Access

TIMER1

TIMER1 Privileged Access

TIMER2

TIMER2 Privileged Access

TIMER3

TIMER3 Privileged Access

USART0

USART0 Privileged Access

USART1

USART1 Privileged Access

USART2

USART2 Privileged Access

BURTC

BURTC Privileged Access

I2C1

I2C1 Privileged Access

CHIPTESTCTRL

CHIPTESTCTRL Privileged Access

LVGD

LVGD Privileged Access

SYSCFG

SYSCFG Privileged Access

BURAM

BURAM Privileged Access

IFADCDEBUG

IFADCDEBUG Privileged Access

GPCRC

GPCRC Privileged Access

RTCC

RTCC Privileged Access

Links

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